1. Field of the Invention
The present invention relates to a microprocessor of the microprogram-controlled type, and particularly to a self-diagnostic test for such a microprocessor.
2. Description of the Related Art
Semiconductor integrated circuits are produced in quantity on a single silicon wafer using photographic techniques. When structural defects occur in the wafer, however, transistors formed at the defective portions will not function, and a semiconductor integrated circuit incorporating such a transistor cannot be expected to function normally. At the present state of the art, structural defects will to a certain level of probability be included in a silicon wafer, and as a result, defective units will inevitably occur among manufactured semiconductor integrated circuits.
In order to avoid shipping the above-described defective units, all manufactured semiconductor integrated circuits must be tested one by one before shipment to ensure that they operate normally. For this purpose, a testing circuit for semiconductor integrated circuits is employed in which test vectors are inputted at the input terminals of the semiconductor integrated circuit, and the output from the output terminals of the semiconductor integrated circuit is compared with previously prepared vectors of expected values.
When test vectors are inputted to the input terminals of a normal semiconductor integrated circuit, the output from the output terminals will coincide with the expected vectors, and therefore, a semiconductor integrated circuit with output differing from the expected vectors is determined to be a defective article containing malfunctioning transistors.
Should a malfunctioning transistor exist in any portion of a semiconductor integrated circuit, test vectors that do not call this transistor into play will not allow discovery of the defect. Therefore, in order that test vectors be effective, it is imperative that all of the semiconductor integrated circuits and logic without exception be caused to operate.
Nevertheless, even should the vectors call a malfunctioning transistor into play, if the effect of the transistor does not arrive at the output terminals of the semiconductor integrated circuit, a difference from the expected vectors will not be noted and the failure of the transistor will not be detected. This type of problem is peculiar to the test vectors itself, and underlines the necessity of rating the quality of test vectors.
One of the criteria of the quality of test vectors is the fault-coverage. The fault-coverage is an index of the ability to determine that an article is defective based on output differing from the expected vectors obtained after inputting test vectors to a semiconductor integrated circuit containing any defective transistor. The fault-coverage is measured by means of fault simulation.
Fault simulation is carried out by intentionally causing the fault of an arbitrary transistor within a semiconductor integrated circuit in order to simulate a defective circuit and determining whether or not differences from the expected vectors occur at the output terminal. This investigation is conducted by repeatedly simulating faults at different points in the semiconductor integrated circuit.
If the number of simulations carried out by causing faults is defined as the number of sampled faults and the number of these faults producing output differing from the expected vectors is defined as the number of detected faults, the fault-coverage can be expressed as [number of detected faults/number of sampled faults]. Ideal test vectors would achieve a fault-coverage of 100% and would be capable of determining as defective a semiconductor integrated circuit having a malfunctioning transistor in any portion.
Recently, however, the trend of semiconductor integrated circuits towards larger scale and greater complexity has resulted in dramatically greater numbers of incorporated transistors and extremely complex internal operations. Because there consequently are included many transistors that are called into play only under special conditions, the effect of these malfunctioning transistors will become apparent at the output of the semiconductor integrated circuit only in rare instances.
With this type of semiconductor integrated circuit, producing test vectors with a fault-coverage of 100% is an extremely laborious process, and in addition, the resulting test vectors will include an unwieldy number of instructions and a test will require a great deal of time to carry out. Accordingly, for the purpose of easily detecting the existence of malfunctioning transistors within semiconductor integrated circuits containing transistors whose fault is extremely difficult to discover, it is common to provide semiconductor integrated circuits with an easily performed self-diagnostic test function.
Currently, nearly all microprocessors composed of semiconductor integrated circuits employ a microprogram control method. In a microprogram control method, a sequence of instruction code (hereinafter referred to as micro instructions) is stored within an internal microprogram read memory (hereinafter referred to as MROM). The microprocessor reads the micro instructions in order by means of control circuits and delivers the instructions to an execute circuit.
Practically, however, the control circuit, in place of the instruction code, reads the address of the MROM corresponding to the instructions and outputs to the execute circuit the sequence of instruction code beginning with this address. A block diagram illustrating the operation of this microprogram control method is presented in FIG. 1.
A microprocessor using a microprogram control method is provided with a micro instruction read memory (to be referred to as MROM) 13a, a first selector 8, a microprogram address register (MAR) 10, an incrementer 7, an instruction decoder 6, an align instruction register (AIR) 5, and logical circuits 4a, 4b, 4c, 4d, 4e, 4f. Macro instructions received by the microprocessor from the outside through an external terminal 1 are transferred to the instruction bus 14 through an input circuit 3 made up of a buffer register or an I/O and stored in the align instruction register 5. The results of computation carried out by logical circuits 4a-4f in accordance with the micro instructions stored in MROM 13a are then transmitted to the external circuit from output circuit 2. The instruction decoder (ID) 6 generates microprogram address S17 in order to read the micro instructions needed to perform the macro instruction. Microprogram address S17 is supplied to the address input of MROM 13a through the first selector 8. The incrementer 7 increments selector output signal S25 by 1, and then generates the next microprogram address (incremented address). The incremented address S21 is stored within the microprogram address register 10. MROM 13a receives selector signal S25 and outputs the corresponding micro instructions S19. These micro instructions S19 are composed of control signal S19b, which actually manipulates the data, and control signal S19a, which is directed to the first selector 8.
The first selector 8 responds to selector control signal S16, which is a portion of control signal S19a, and selects any one of the following: the microprogram address indicated by output S21 of the microprogram address register 10, microprogram address S17 supplied from the instruction decoder 6, and address signal S18 which is one field of control signal S19a. If address signal S18 does not designate a microprogram address, the first selector 8, controlled by selector control signal S16, selects the output of the microprogram address register 10. Accordingly, the address input of the MROM 13 becomes the succeeding microprogram address. In cases where address signal S18 designates a microprogram address, the micro instructions S19 corresponding to that address are read from MROM 13 and the microprocessor processes the data in accordance with control signal S19b contained within the micro instructions S19 and output S21 of the microprogram address register 10 is incremented by 1. This operation is iterated, and when address signal S18 is about to stop designating microprogram addresses, the first selector 8, under the control of selector control signal S16, selects output S21 of the microprogram address register 10, and the input of MROM 13a becomes microprogram address S21 created through incrementation. In this way, the micro instructions are successively processed.
When the microprogram corresponding to the inputted macro instruction is completed, the first selector 8 selects microprogram address S17 provided by the instruction decoder 6, and begins processing the macro instruction supplied from the outside. The macro instruction is defined by a plurality of micro instructions and is realized by the ordered execution of the micro instructions.
Since micro instructions are defined in much finer detail than a macro instruction, they can control the internal state of the microprocessor in ways that a macro instruction cannot and can control the operations of transistors that cannot be operated in normal operation. Consequently, self-diagnostic tests are widely carried out in microprocessors using these micro instructions.
FIG. 2 (encompassing FIGS. 2A and 2B) is an operation flow chart illustrating the operation of the blocks in FIG. 1. First, the microprocessor is reset (step 41) and the minimum necessary initialization is carried out (step 42), after which the microprocessor begins normal operation.
When a self-diagnosis instruction, which is applied as a macro instruction from external terminal 1, is stored in the align instruction register 5 by way of the input circuit 3 and the instruction bus 14, microprogram address S17 of a self-diagnosis microprogram is generated by means of the instruction decoder 6.
This microprogram address S17 is selected by the first selector 8, delivered to MROM 13a which stores microprogram instructions, and a microprogram (MP) read from that address is executed (step 43). In other words, control signal S19b supplied from MROM 13 is transmitted to each portion of the microprocessor.
The microprogram used in this micro self-diagnosis supplies the data built into the microprogram to logical circuit 4a made up of a register, a logical operation circuit, etc., which are the subjects of this microprocessor test, initiates the logical operation (step 44), and then compares the results with the expected value provided in the microprogram to determine whether or not they agree (step 45). If the values do not agree, the execution of the self-diagnostic instruction is interrupted at this point and the abnormality code is written to the diagnosis result register (DRR) in the microprocessor (step 46). The microprocessor then returns to normal operation.
If the results of this comparison show agreement, the same test is performed on logical circuit 4b which is the subject of the next test (step 47). When the self-diagnostic instructions have been carried out, the normality code is written to the above-described diagnosis result register (step 48) and the microprocessor returns to normal operation. When the self-diagnosis macro instruction has been completed, the microprocessor transmits the contents of the diagnosis results register to a memory outside the microprocessor (step 49) and checks the results of the self diagnosis (step 40).
This method allows testing of the signals within the microprocessor with virtually no need for adding special testing hardware and enables verification from the outside of the state of components which are extremely difficult to check during normal operating conditions.
However, this self-diagnostic microprogram must be established in the design of the microprocessor, and consequently, when revising the microprogram to allow more detailed detection and a higher fault-coverage, it is necessary to modify the design of the microprogram provided in the microprocessor. As a result, the self-diagnostic microprogram may not be easily added to or modified.
Next will be considered the microprocessor defect analysis. When the quality of a microprocessor has been judged as inferior, it is necessary to employ a semiconductor testing circuit by which various data are applied to an external terminal of the microprocessor, and based on the output produced by the microprocessor in performing a series of elementary operations or a series of micro steps designated by one or more test instructions, the defective point in the hardware is analyzed. In this analysis, however, there is no alternative to depending on the output of the microprocessor as a basis for investigating and making inferences, and this severely complicates the pinpointing of a faulty micro step causing the malfunctioning of the microprocessor.
As a solution to this problem, there is the WCS (Writable Control Store) method in which the microprogram read memory is made into RAM to render the microprogram alterable. In this method, when control over a detailed operation of the interior of the microprocessor is desired, such as in defect analysis, it is possible to write a microprogram from the outside and execute it in order to allow the effective performance of defect analysis.
The conventional microprocessors described above have problems which will be set forth below.
Because it is generally very difficult to raise the fault-coverage, it is usual to incorporate into the microprocessor a circuit for judging the state of the microprocessor itself. In this case, test logic using a microprogram is employed in order that there be nearly no increase in the amount of hardware. However, even with this method, it is extremely difficult to create a microprogram for testing that will enable a superior fault-coverage rate and a speedy defect analysis. Fundamentally, it is preferable that a microprogram for testing be designed at the time the microprocessor itself is designed, but because the design of a good microprogram for testing is extremely time-consuming, it is the common practice to begin preparing and revising a microprogram for testing only after the microprocessor has been produced. However, revisions of a microprogram entail the necessary revision of the microprocessor hardware itself as well as the redesign of the microprocessor, at a considerable expense of time and labor. Further, since it is necessary in the conventional method to store the test data for testing the microprocessor in the MROM, the provision of sufficient data for testing leads to the problem of an unwieldy MROM.
With regard to defect analysis of the microprocessor, since conventional testing methods only provide the results of a series of micro steps designated by one or more test instructions and not the result of an individual micro step, only the absence or existence of a defect can be determined. If an abnormality is discovered in an early test item among the test instructions, it will remain unknown whether the following tests provide correct results or not. In addition, there is the problem that for defects that cannot be discovered by tests based on the provided data, the tests serve no purpose.
The testing method of making the microprogram read memory RAM and then writing and executing the testing microprogram from the outside allows effective execution of the defect analysis, but there is the problem that the necessity for hardware for writing to the microprogram read memory increases the amount of hardware. In addition, RAM takes more area on a substrate than ROM, increasing the area necessary for the microprocessor. In order to actually start a self-diagnostic test, there is also the problem of the time required to write all of the test microprograms before the self-diagnosis can begin.